A Scalable Patterning Method for High-Performance Electronic Devices

Student’s name: Ryugo Shimamura Home institution: The University of Tokyo NNCI site: SENIC @ Georgia Institute of Technology REU Principal Investigator: Dr. Michael Filler and Dr. Eric Vogel - Georgia Institute of Technology REU Mentor: Daniel Aziz - Georgia Institute of Technology Abstract: Rapid progress in semiconductor technology relied on miniaturization of transistors, but as channel dimensions approach the atomic scale, efforts for miniaturization are becoming less economic. Using doped silicon nanowires (SiNW) as electronic components is a viable option, since they can be produced in a massively parallel manner. To realize this concept, patterning methods that allow for surface functionalization of SiNW sidewalls are essential, but since conventional photolithography methods are not compatible with scalable parallel manufacturing, novel methods are needed. Promising results has been shown using PMMA polymer, combined with a doping-dependent etching of Silicon that allows PMMA to be removed from less doped regions selectively. This work covers three contributions. First, relationship between SiNW growth conditions and selectivity of etching is presented. Substrates for growth, gas flow rate and growth temperature are the key factors to a successful patterning. Secondly, a design for testing SAM(Self-Assembled Monolayer)-initiated polymerization effectively, which incorporates multiple characterization schemes such as scanning electron microscopy (SEM), atomic force microscopy (AFM), reflectometry and ellipsometry has been created. Lastly, analysis of polymer removal from differently doped silicon will be presented to show masking of desired regions. Above contributions will enhance understanding of key processes, promising to build a foundation for scalable patterning of electronic nanostructures.